Charge pumps are commonly used in flash and other types of memory devices to provide voltages outside of the range of ground to the power supply voltage. In some flash memory devices, charge pumps are used to generate large negative voltages, such as -11 V, to erase or program memory cells. Other flash memory devices use large positive voltages to erase or program memory cells.
An eight stage charge pump using a four phase clock is illustrated in FIG. 1. The charge pump system is comprised of eight charge pump stages 110-117, an output circuit 118, and a four phase clock generator 119. The four clock signals generated by clock 119 are labeled .phi.1, .phi.1A, .phi.2 and .phi.2A. The eight charge pumps are connected in series so that the output of each charge pump provides a larger magnitude output voltage than the previous charge pump. The charge pump system of FIG. 1 is a negative charge pump system. A conventional circuit for charge pump stages 110-117 is illustrated FIG. 2. A conventional circuit for output stage 118 is illustrated in FIG. 3. A timing diagram of the clock signals in the charge pump system is shown in FIG. 4.
The charge pump system of FIG. 1 transfers negative charge from one charge pump stage to the next charge pump stage, and ultimately to NOUT 132. The system also transfers positive charge back through preceding charge pump stages to ground. The FIG. 2 charge pump circuit includes clock terminals OCK 220 and GCK 222, capacitor configured PMOS transistors P204 and P205 coupled to the clock terminals, PMOS pass transistor P201 coupled to IN 226 and OUT 224, and diode configured pull-down PMOS transistor P206. In operation, at stage 114 when the .phi.1 clock signal coupled to OCK 220 goes high at time t3 shown in FIG. 4, positive charge is coupled through the large capacitor formed by capacitor configured PMOS transistor P205 to node 224. At this time, the clock signal coupled to GCK 222 is low and PMOS pass transistor P201 is on. Positive charge is thereby coupled through transistor P201 and IN 226 to the preceding charge pump stage, stage 113.
When the .phi.2A clock signal goes high at GCK 222 in stage 114 at time t5, positive charge is coupled through the small capacitor formed by capacitor configured PMOS transistor P204. This positive charge increases the voltage of node 210 and turns off PMOS pass transistor P201. When the positive charge coupled through P204 increases the voltage of node 210 beyond a threshold voltage above the OUT 224 voltage, this turns on PMOS transistor P203. Transistor P203 couples the excess positive charge from node 210 to IN 226. The positive charge is incrementally coupled through each of the preceding charge pump stages and eventually to ground. Transistor P203 turns off when the node 210 voltage is reduced to within a threshold voltage of the OUT 224 voltage. At this point the node 210 voltage is still high enough to keep transistor P201 off.
When the .phi.1 clock signal goes low at OCK 220 in stage 114 at time t6, it couples negative charge to node OUT 224. With transistor P201 off this negative charge is coupled to the next charge pump stage, stage 115, through OUT 224. This process of transferring positive charge to the preceding stage, and negative charge to the next stage is repeated at each charge pump stage.
The conventional output stage 118 illustrated in FIG. 3 includes PMOS pass transistor P301, three diode configured PMOS transistors P307-P309, a capacitor configured PMOS transistor P302 and a discharge PMOS transistor P303. In operation when the OCK clock signal at the preceding charge pump stage goes low, for example, signal .phi.2 at time t2 shown in FIG. 4, this couples negative charge to the IN 324 node. This negative charge is coupled through diode configured transistor P303 to pre-charge node 310. Node 310 is thereby pre-charged down to a diode drop above the IN 324 voltage. At time t4, when the .phi.2A signal goes low, this couples negative charge to node 310. The drop in the node 310 voltage turns PMOS pass transistor P301 on which allows the negative charge from IN 324 to pass through to OUT 326. At time t5 .phi.2A goes high at the output stage GCK terminal. This couples positive charge to node 310. When the node 310 voltage rises a threshold voltage above the IN 324 voltage, PMOS transistor P303 turns on. Node 310 then discharges through transistor P303 until the node 310 voltage is brought up to a threshold voltage below the IN 324 voltage. This process is repeated, and after a number of clock cycles, a large negative output voltage is provided at NOUT 132.
As the magnitude of the negative output voltage increases in the charge pump, the junction breakdown voltage limits the output voltage range. The voltage at the gate, node 310, of PMOS pass transistor P301 must be a threshold voltage below the OUT 326 voltage to turn transistor P301 on. The threshold voltage V.sub.T for PMOS transistors increases with the bulk (substrate) to source voltage according to the equation V.sub.T =V.sub.TO -g(sqrt(.phi.+V.sub.BS)-sqrt(.phi.)), where V.sub.BS is the bulk to source voltage, V.sub.TO is threshold voltage for V.sub.BS =0, g is the bulk threshold parameter and .phi. is the strong inversion surface potential. As the negative output voltage at each stage is increased the bulk to source voltage increases, and therefore a larger negative voltage is required at the gate of transistor P301 to turn the transistor on. Furthermore, to drive the output voltage negative quickly the node 310 voltage should be driven lower than the threshold voltage. In one semiconductor process, the junction breakdown voltage is -13 V. The node 310 voltage is then self-limited to -13 V. With a threshold voltage of -2.5 V, the conventional output stage of FIG. 3 would be unable to provide a -11 V OUT 326 voltage because of the inability to drive node 310 beyond -13 V. The junction breakdown voltage limits the current drive capability of PMOS transistor for output voltages near -11 V because of the inability to provide a sufficiently large overdrive voltage at node 310. Attempts to drive node 310 to a negative voltage larger than -13 V could cause the p+ source to n-well junction of PMOS transistor P303 to breakdown, which could in turn cause a latch-up condition or an operational error.
Thus an improved charge pump stage that overcomes these and other problems of the prior art would be highly desirable.